Microsoft SP5100/S manuels

Microsoft SP5100/S Spécifications (74 pages)

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Table des matières

AMD SP5100

1

Register Programming

1

Requirements

1

Table of Contents

3

1 Introduction

7

2.3 WakeIO Base Address

10

Page 11

11

Page 12

12

Page 13

13

Page 14

14

2.11 Sx State Settings

15

2.10 Therm Trip Settings

15

2.13 SUS_STAT# Enhancement

16

2.15 IO Trap Settings

17

2.18 USB Set BM_STS

18

2.20 PCIe

19

Native Mode

19

2.21 Hardware Monitor

19

2.22 Cir Interrupt Config

20

2.23 SMBUS PCI Config

20

2.24 IMC Access Control

20

2.25 CPU Reset

21

2.30 Revision ID

23

2.32 Gevent5 as GPIO

24

2.34 SMBUS Sequence

25

Page 27

27

2.42 HPET MSI Setting

28

2.43 SMAF Matching Setting

29

3.1 IO / Mem Decoding

30

3.2 SPI Bus

30

4.1 Defining AB_REG_BAR

31

4.2 Clearing AB_INDX

31

4.5 OHCI Prefetch Settings

32

Arbitration Equation

33

Posted Transactions

34

4.14 Enabling Requester ID

35

4.16 SMI IO Write

36

Page 37

37

Page 38

38

5.5 Master Latency Timer

39

5.6 DMA Read Command Match

39

5.8 GNT# Timing Adjustment

40

Page 41

41

5.14 Adjusting CLKRUN#

42

~02/ bus-0, dev-20, fun-05)

43

Page 44

44

6.5 USB Reset Sequence

45

Page 46

46

6.15 EHCI Async Park Mode

48

6.20 Async Park Mode

50

6.21 Resume Reset Timing

50

6.22 Disable Async QH Cache

50

6.25 USB PID_ERROR_CHECKING

52

7 SATA: dev-17, func-0

53

7.3 Disabling SATA

54

SATA: dev-17, func-0

55

Page 55

55

7.7.1 SATA Drive Detection

58

Page 59

59

LPC (bus-0, dev-20, fun-03)

63

Page 63

63

Page 66

66

Appendix B: Revision History

72

Page 73

73

Page 74

74

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