Microsoft AGB-00001 Spécifications télécharger pdf (Page 116)

VHDL for the ABEL-HDL Designer

C-4 VHDL Reference Manual

s1,s0 pin istype 'com'; "sum

c0,c1 pin istype 'com'; "carry bits

equations

c0 = b0 & a0; " carry from bit 0

s0 = b0 $ a0; " sum of bit 0

c1 = b1 $ a1; " carry out

s1 = b1 $ a1 $ c0; " sum for bit 1

end

Describing Combinational Logic in VHDL

In VHDL, you can describe combinational logic using concurrent

statements in the architecture section of your program. The following

is a VHDL architecture describing the same adder:

architecture adder of add is

begin

c0 <= b0 and a0; -- carry from bit 0

s0 <= b0 xor a0; -- sum for bit 0

c1 <= b1 xor a1; -- carry out

s1 <= b1 xor a1 xor c0; -- sum for bit 1

end adder;

Registers

Describing Registers in ABEL-HDL

In ABEL-HDL, you can describe registered circuit elements by

specifying the various flip-flop inputs, such as clocks, resets and data

through the use of dot extensions like .CLK, .AR, and .D. ABEL-HDL

also allows you to write registered output functions using pin-to-pin

syntax through the use of a registered assignment (:=). Using pin-to-

pin syntax, a D flip-flop is described in ABEL-HDL as:

foo.CLK = clock;

foo := Data # Preset

Describing Registers in VHDL

In ABEL-HDL, you specify registers when you supply inputs to register

macrocells that are inherently predefined in the language. In VHDL,

however, there is no inherent register behavior or macrocell, unless

one has been provided (written in VHDL as a procedure or component,

or implied by the defined behavior of a VHDL process). There is also no

direct equivalent in VHDL to ABEL-HDL's register assignment

statement. In VHDL, your description of registered operation will differ

depending on whether you are using structural, dataflow or behavioral

design methods. In structural or dataflow VHDL, your program must

define how the flip-flop operates. In behavioral VHDL, the actual flip-

flops can be implied, rather than specified.

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