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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
VHDL for the ABEL-HDL Designer
C-12 VHDL Reference Manual
end if;
end process;
process (Clk,OE,Count) -- Counter
begin
if rising_edge(Clk) then -- Edge triggered
if Clr = '1' then
Count <= 0;
elsif Count = 15 then
Count <= 0;
else
Count <= Count + 1;
end if;
end if;
if OE = '1' then
Q <= "ZZZZ"; -- Make Q high Z
else
Q <= To_Vector(4,Count);
end if;
end process;
end example;
Design I/O
In this design, the I/O ports are assigned to pins as described earlier in
this chapter. (This design is intended for implementation in a 20-pin
PLD such as an Altera E0320.) Std_logic_vectors A and B represent
two bidirectional buffers controlled by the Dir input. The convention for
defining an output enable function in VHDL is to specify an assignment
to 'Z' for the disabled state. In this design, A, B and Q all have output
enable functions defined using 'Z'.
Combinational Logic
The combinational logic for A and B is defined in a process statement,
but could just as easily have been defined using concurrent
statements. (Whether to use concurrent statements or sequential
statements for combinational logic is largely a matter of personal
taste.) When a process statement is used to define a combinational
logic function, all of the inputs to that logic function must be entered in
the sensitivity list. In this case, the three inputs are Dir, A and B.
Registered Logic
The counter portion of this design is described in the second process
statement. This process statement includes both Clk and OE in its
sensitivity list because the output enable control for Q is not
dependent on the clock. The sensitivity lists for a process must contain
all inputs that are to be processed asynchronously. To provide a
clocking function for the counter, the counter logic is contained in an if
statement that describes the clock input using the previously described
convention for edge triggered flip-flop behavior.
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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