Microsoft AGB-00001 Spécifications télécharger pdf (Page 121)

VHDL for the ABEL-HDL Designer

VHDL Reference Manual C-9

State Machines

Describing State Machines in ABEL-HDL

In ABEL-HDL, you describe a state machine similar to the way you

create a behavioral model in VHDL. You create a state description for

each possible state of the machine, beginning each with a description

of the state value to be stored in the state registers. For example:

module st_mach

q1,q0 pin istype 'reg';

A,B pin istype 'com';

equations

[q1,q0].clk = clock;

state_diagram [q1,q0]

state [1,1]:

A = 1; "A is high in this state

B = 1; "B is high in this state

if (start)

then [1,1] "Hold state

else

goto [0,0]; "Transition to 0,0

end st_mach

In ABEL-HDL, you must specify the actual registers that are used (in

this case, q0 and q1) and the values to be stored in those registers

when in each state.

ABEL-HDL state diagrams are normally accompanied by one or more

equations describing the clock, reset or other additional functions for

the state registers.

Describing State Machines in VHDL

In VHDL, you write a behavioral model for the state machine,

typically by adding an if-then conditional statement and a case

statement inside of a process statement in your program. To more

clearly distinguish the clock logic of state machines (the registered

portion) from the transition logic (the combinational logic portion), it is

good practice to use two process statements as shown in the following

example. In this example, the first process describes the registered

behavior of the state machine, while the second process describes the

transition logic, and the combinational output logic for the machine:

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Microsoft AGB-00001 Spécifications Page 121