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VHDL Reference Manual 2-1

2. Language Structure

VHDL is a hardware description language (HDL) that contains the

features of conventional programming languages such as Pascal or C,

logic description languages such as ABEL-HDL, and netlist languages

such as EDIF. VHDL also includes design management features, and

features that allow precise modeling of events that occur over time.

This chapter introduces a subset of the VHDL language that allows you

to begin creating synthesizable designs, and is not intended to

describe the full language. For further information on VHDL, consult a

standard VHDL reference book. A number of these books are listed at

the end of this chapter.

The VHDL Synthesizer supports most of the VHDL language, as

described in IEEE Standard 1076-1993. The meaning of some sections

of the language, however, is unclear in the context of logic synthesis.

Examples of this are found in the standard package textio. The file I/O

operations supported by textio are useful for simulation purposes but

are not currently synthesizable.

• For sample syntax and a list of VHDL statements supported by the

VHDL Synthesizer, see Appendix A, “Quick Reference.”

• For a list of exceptions and constraints on the VHDL Synthesizer's

support of VHDL, see Appendix B, “Limitations.”

This chapter shows you the structure of a VHDL design, and then

describes the primary building blocks of VHDL used to describe typical

circuits for synthesis:

• Library (Design) Units

• Statements

• Objects

• Types

• Operators

• Attributes

In addition, the three primary methods of VHDL design are discussed:

• Dataflow VHDL

• Behavioral VHDL

• Structural VHDL

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Microsoft AGB-00001 Spécifications Page 9