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How to Manage VHDL Design Hierarchies
6-2 VHDL Reference Manual
Components
VHDL design entities can be referenced from other architectures as
components. VHDL allows you to manage the mapping of design
entities to components with a configuration specification (described in
the next section) that associates particular component instances with a
specified design entity. In most cases, however, you will have only one
design entity for each component instance, and you will simply let the
VHDL synthesizer (or simulator) select the default entity (default
binding) for each component.
The following example contains three entity/architecture pairs: two
lower level entities (add and mult) and a top level entity (addmult)
that includes two component instantiations of the lower-level entities:
-----------------------------
-- lower-level entity: adder
--
entity add is
port(op1,op2: in integer range 0 to 7;
result: out integer range 0 to 63);
end add;
architecture dataflow of add is
begin
result <= op1 + op2; -- add the operands
end dataflow;
----------------------------------
-- lower-level entity: multiplier
--
entity mult is
port(op1,op2: in integer range 0 to 7;
result: out integer range 0 to 63);
end mult;
architecture dataflow of mult is
begin
result <= op1 * op2; -- multiply the operands
end dataflow;
------------------------------------------------------
-- top-level entity: mux of add and multiply results
--
entity addmult is
port(op1,op2: in integer range 0 to 7; sel: in boolean;
result: out integer range 0 to 63);
end addmult;
architecture structure of addmult is
signal s_add, s_mult: integer range 0 to 63;
component add -- component declaration
port(op1,op2: in integer range 0 to 7;
result: out integer range 0 to 63);
end component;
component mult -- component declaration
port(op1,op2: in integer range 0 to 7;
result: out integer range 0 to 63);
end component;
begin
add1: add port map (op1,op2,s_add);
mult1: mult port map (op1,op2,s_mult);
with sel select -- Mux the add and multiply results
result <= s_add when FALSE,
s_mult when TRUE;
end structure;
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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