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Noté. / 5. Basé sur avis des utilisateurs
How to Control the Implementation of VHDL
4-18 VHDL Reference Manual
Enum_encoding Attribute
The enum_encoding attribute allows you to override the default
encoding of VHDL enumerated types. This is most useful when you
want to specify a non-sequential encoding for an enumerated type. For
example, you might want to use enum_encoding to specify the exact
encoding of each state in a state machine. The enum_encoding
attribute can also be used to encode don’t-care information into the
logic of an enumerated type output, or can be used to define
synthesizable 1-bit values for a multi-valued data type (such as the
IEEE 1164 type std_ulogic).
The syntax for the enum_encoding attribute is demonstrated in the
following example, which specifies an alternate encoding for a state
machine. To use the enum_encoding attribute, you must first define
it as a string type:
attribute enum_encoding: string;
and then write an attribute statement for the desired encoding values:
architecture behavior of state_machine is
type state_values is (Init, S1, S2, S3, S4, S5);
attribute enum_encoding: string;
attribute enum_encoding of state_values: type is
"000 001 011 111 110 100";
A special enum_encoding string, "one hot", can be used to specify
that an enumerated type represents a list of symbolic state machine
states, and is to be encoded using a one register per state (one hot)
encoding method. This method is particularly useful for state machines
that will be implemented in FPGA devices, and results in less
combinational logic being required for state decoding. The syntax for
the one hot encoding attribute is:
architecture behavior of state_machine is
type state_values is (Init, S1, S2, S3, S4, S5);
attribute enum_encoding: string;
attribute enum_encoding of state_values: type is
"one hot";
An example of one hot state encoding can be found in the tutorials
chapter in the VHDL Entry manual, in the complex state machine
example.
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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