Microsoft AGB-00001 Spécifications télécharger pdf (Page 19)

Language Structure

VHDL Reference Manual 2-11

Data Types

VHDL supports a variety of data types. The type of a variable, signal,

or constant determines the operators that are predefined for that

object as well as the range of values that it can take on.

The predefined VHDL data types include:

• numeric (integer or real)

• boolean

• character

• time (measured in units from fs to hr)

• string (an array of characters)

• bit (can have a value of 0 or 1)

• bit_vector (an array of bits)

After the language was defined it was acknowledged that the built-in

types were not entirely adequate for modeling the behavior of real

hardware. The IEEE standard 1164 was developed to address this

shortcoming. This standard defines the types:

• std_ulogic and std_logic (the equivalent of bits but with 9 possible

data values instead of two)

• std_ulogic_vector and std_logic_vector (an array of std_ulogic and

std_logic, respectively)

Definitions for all of the predefined types, with the exception of

std_logic and std_logic_vector, are in the file std.vhd, which contains

the package standard. The types created by the 1164 standard are

defined in the file ieee.vhd. The primary difference between std_ulogic

and std_logic is that std_logic is what is referred to as a resolved type.

This means that objects of type std_logic can be used for modeling

logic with multiple drivers, such as tristate buses or wired logic.

Objects of type std_ulogic may have only one driver.

In addition to types, subtypes may be used to define subsets of their

base type. For example, a short integer type (one with a specified

maximum value) can be defined as a subtype with the statement:

subtype short_int is integer range 0 to 255;

VHDL also supports enumerated and user-defined types, which are

explained later in this section.

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Microsoft AGB-00001 Spécifications Page 19