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Noté. / 5. Basé sur avis des utilisateurs
Language Structure
VHDL Reference Manual 2-7
Concurrent statements include the following:
• Signal assignments (selected and conditional)
• Component instantiations
• Generate statements
• Process statements
• Procedure and function calls
The following syntax shows an example of an architecture declaration
with concurrent statements. Note that this code fragment also
demonstrates how to include comments in VHDL source code. The
double-hyphen character sequence (--) always begins a comment, and
the comment continues until the end of the line.
architecture dataflow of my_circuit is
signal d,e bit;
begin
-- concurrent statements tied together with signals
d <= in3 and in4; -- logic for d
e <= in5 or in6; -- logic for e
out1 <= in1 xor d; -- output logic
out2 <= in2 xor e; -- output logic
end dataflow;
Sequential Statements
Sequential statements differ from concurrent VHDL statements in that
they are executed in the order they are written. Sequential statements
always appear within a process statement (which, in its entirety, is a
concurrent statement) or within a function or procedure.
Sequential statements are similar to statements used in software
programming languages such as C or Pascal. The term sequential in
VHDL refers to the fact that the statements execute in order, rather
than to the type of logic generated. That is, you can use sequential
statements to describe either combinational or sequential (registered)
logic. With sequential statements, values may be carried using either
signals or variables.
Sequential statements include the following types of statements:
• Variable declarations
• Signal assignments
• Variable assignments
• Procedure and function calls
• If, case, loop, next, exit, return statements
• Wait statements
Following is an example of an architecture declaration that includes
sequential statements in a process statement:
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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