Microsoft AGB-00001 Spécifications télécharger pdf (Page 63)

How to Control the Implementation of VHDL

VHDL Reference Manual 4-5

type cpu_op is (execute,

load, store);

Two wires with the values 00, 01, and

10; the binary encoding 11 is a don’t-

care.

subtype mem_op is

cpu_op

range load to store;

Two wires with the values 01 and 10;

the encodings 00 and 11 are don’t-

cares.

Describing Output Enables

Output enables are commonly used in PLD-based designs, but the

VHDL language does not define an explicit output enable function such

as that found in ABEL-HDL or other PLD and FPGA oriented languages.

To describe an output enable, you must write your VHDL design using

the special enumerated value Z and the IEEE 1164 std_logic data

type, or some other enumerated type that includes Z as a possible

value.

Using Std_logic to Describe Output Enables

VHDL does not provide an explicit method for describing a signal that

can be disabled, so various conventions have been adopted for this

purpose. The most common way to describe a three-state signal is to

use the IEEE 1164 std_logic data type, which includes a value of Z as

one of its possible values. The following design uses the std_logic

data type, and describes the disabled state of the output using the Z

constant:

library ieee;

use ieee.std_logic_1164.all;

package example_bus is

subtype bundle is std_logic_vector (0 to 4);

end example_bus;

use work.example_bus.all;

library ieee;

use ieee.std_logic_1164.all;

entity tbuf is

port (enable: in std_logic; a: in bundle;

m: out bundle);

end tbuf;

architecture example of tbuf is

begin

process (enable, a)

begin

if enable = '1' then

m <= a;

else

m <= "ZZZZZ";

end if;

end process;

end example;

Note: Output enables generated by the VHDL synthesizer correspond

to the three-state output pins found in most PLD and FPGA devices.

They do not correspond to internal tri-states such as those found in

Xilinx FPGAs.

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Microsoft AGB-00001 Spécifications Page 63

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