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Noté. / 5. Basé sur avis des utilisateurs
Language Structure
VHDL Reference Manual 2-15
process(clk)
begin
if clk and clk'event then
p <= p + 1;
end if;
end process;
end behavior;
In this example, type integer was used because the "+" operator is
defined for integers but not for bit_vectors.
The most common user-defined types are enumerated types, described
in the previous section.
Types and Logic Synthesis
In VHDL, types are used for type checking and for operator overload
resolution (a situation in which two or more operators or functions
have the same name, but specify different argument types). For logic
synthesis, each type declaration also defines the encoding and number
of wires to be generated. For subtypes, checking and overloading use
the base type of the subtype. Each subtype declaration defines a
subset of its base type and can specify the number or wires (directly or
indirectly) and possibly the encoding scheme.
During compilation, ports with types that synthesize to multiple wires
are renamed by appending _n_, where n is an incremented integer
starting from zero.
Type Conversions
Because VHDL is strongly typed, and not all operations are supported
for all standard data types, and it is sometimes necessary to convert
from one type to another. A good example of this is the previous
example, which used an integer data type to describe a counter. What
if the design required (for external interface reasons) that all I/O ports
be of type std_logic? Since there is no pre-defined + operator for non-
numeric types such as std_logic, it is necessary to either overload the
+ operator (by writing a new + function for std_logic_vector data
types) or convert the type from std_logic_vector to integer, and then
from integer back to std_logic_vector as shown below:
library ieee;
use ieee.std_logic_1164.all;
entity counter is
port (clk: in std_logic;
p: inout std_logic_vector(1 downto 0);
end counter;
library dataio;
use dataio.std_logic_ops.all;
architecture behavior of counter is
begin
process (clk)
begin
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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