How to Control the Implementation of VHDL
VHDL Reference Manual D-3
Dot
Ext.
Pin-to-
pin
Description
.COM ü A combinational feedback from the flip-flop
data input, normalized to the pin value and
used to distinguish between pin (.PIN) and
internal logic array (.COM) feedback.
.D When on the left side of an equation, .D is
the data input to a D-type flip-flop; on the
right side, .D is combinational feedback.
.FB ü Register feedback
.FC Flip-flop mode control
.J J input to a JK-type flip-flop
.K K input to a JK-type flip-flop
.LD Register load input
.LE Latch-enable input to a latch
.LH Latch-enable (high) to a latch
.OE ü Output enable
.PIN ü Pin feedback
.PR Register preset (synchronous or
asynchronous)
.Q Register feedback
.R R input to an SR-type flip-flop
.RE Register reset (synchronous or
asynchronous)
.S S input to an SR-type flip-flop
.SET ü A device-independent synchronous register
preset, equivalent to .SP with ISTYPE
'buffer'.
.SP Synchronous register preset
.SR Synchronous register reset
.T T input to a T-type (toggle) flip flop
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