Microsoft AGB-00001 Spécifications Page 120
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
VHDL for the ABEL-HDL Designer
C-8 VHDL Reference Manual
Perhaps the most common mistake that is made by new VHDL users
(who have had experience with PLD-oriented languages) is the
assumption that unspecified conditions will have no effect on the logic
of the generated circuit. Perhaps the most common example of this is
in the use if conditional assignments within process statements.
Consider, for example, the following VHDL description of the same
multiplexer just presented:
entity mux is
port (s0,s1,a0,a1,b0,b1,c0,c1: in bit; --inputs
y1,y0: out bit); --output Y
end mux;
architecture behavior of mux is
begin
process(s0,s1,a0,a1,b0,b1,c0,c1)
begin
if (s1,s0) = "11" then
(y1,y0) <= (a1,a0);
elsif (s1,s0) = "10" then
(y1,y0) <= (b1,b0);
elsif (s1,s0) = "01" then
(y1,y0) <= (c1,c0);
end process;
end
This design description is also incompletely specified; no value is
specified for the condition in which y1 and y0 are both low. Unlike the
ABEL-HDL version of this circuit, however, the rules of VHDL dictate
that the value of the outputs must be held over time, rather than
transition to a low state. For this design, the circuit that results must
include a latch, and the VHDL synthesizer will construct this latch by
feeding back the outputs to create an asynchronous feedback loop.
To prevent the creation of unwanted latches, you must make sure to
include all of the possible input conditions in your design descriptions.
In the case of conditional assignments such as the multiplexer, you
should include a terminating else statement that defines the default
value:
if (s1,s0) = "11" then
(y1,y0) <= (a1,a0);
elsif (s1,s0) = "10" then
(y1,y0) <= (b1,b0);
elsif (s1,s0) = "01" then
(y1,y0) <= (c1,c0);
else
(y1,y0) <= "00";
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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