Limitations
B-2 VHDL Reference Manual
• A process sensitivity list must contain all signals that the process is
sensitive to.
Constrained Expressions
Certain expressions metalogic expressions which simply means they
evaluate to a constant value, and are not dependent on a signal (they
do not change over time).
• Operands of ** must be metalogic expressions.
• Assignments to elements of an array must have an index that is a
metalogic expression.
• An assertion statement condition, severity, and message must
consist of metalogic expressions, if the message is to be reported.
• Type and subtype declarations must be metalogic expressions.
• Floating point and physical types are constrained to the same set of
values as the equivalent integer type.
• While loop and unconstrained loop execution completion must
depend only on metalogic expressions.
Ignored Constructs
The following constructs are ignored. They may be included in the
VHDL file for simulation purposes, but the VHDL compiler will not
generate any logic for them.
• Disconnect specifications
• Resolution functions
• Signal kind register
• Waveforms, except the first element value
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