Microsoft AGB-00001 Spécifications télécharger pdf (Page 54)

How to Write Synthesizable VHDL

3-28 VHDL Reference Manual

Types of State Machines

Classical state machines can be classified as Moore or Mealy machines.

In a Moore machine, the output is a function of the current state only,

and can change only on a clock edge. Mealy machines, on the other

hand, have outputs that are a function of the current state and the

current inputs. The outputs of a Mealy machine may change when any

input changes.

Moore Machine

In the following architecture, F1 and F2 are combinational logic

functions of an arbitrary complexity. A simple state machine

implementation maps each block to a VHDL process:

library ieee;

use ieee.std_logic_1164.all;

entity system is

port (clock: in std_logic;

A: in std_logic;

D: out std_logic);

end system;

architecture moore1 of system is

signal B, C: std_logic;

begin

F1: process (A, C) -- Next state logic

begin

B <= F1(A, C);

end process;

F2: process (C) -- Output logic

begin

D <= F2(C);

end process;

begin

if rising_edge(clock) then

C <= B;

end if;

end process;

end moore1;

A block diagram that shows how the three processes of this

architecture are related is shown in Figure 3-6.

Figure 3-6: Moore State Machine

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Microsoft AGB-00001 Spécifications Page 54