Microsoft AGB-00001 Spécifications télécharger pdf (Page 44)

How to Write Synthesizable VHDL

3-18 VHDL Reference Manual

process(clk)

begin

if rising_edge(clk) then

y <= a;

end if;

end process;

In all these cases, the number of registers or the width of the mux are

determined by the type of the signal y.

Wait Statement

The second method uses a wait statement within the process:

process

wait until expression;

end process;

This statement suspends evaluation (over time) until an event occurs,

and the expression evaluates to true. When a wait statement is used

in a process, no process sensitivity list is required (or allowed). A flip-

flip may be described as:

process

wait until clk'event and clk='1'

y <= a;

end process;

A constraint of the VHDL synthesizer is that wait statements must be

located at either the beginning or end of a process, and there may not

be more than one wait statement in a process.

Note: Wait statements are not recommended for use in synthesizable

designs. If-then conditional statements are a more universally

accepted method of describing registered logic.

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Microsoft AGB-00001 Spécifications Page 44