How to Write Synthesizable VHDL
VHDL Reference Manual 3-19
Latches
The following three examples each describe a level sensitive latch with
an and function connected to its input. In all three of these examples
the signal y retains its current value unless the clock input (clk) is
high.
Example 1:
This example uses a process statement and conditional (if)
statement. The sensitivity list contains the clock input and two data
inputs because when clk is high the output y changes asynchronously
with any change in a or b:
process (clk,a,b)
begin
if clk='1' then
y <= a and b;
end if;
end process;
Example 2:
This example uses a procedure statement in combination with a
concurrent procedure call. In this example the procedure is called
twice to generate two latches from the declared procedure:
architecture dataflow of latch is
procedure my_latch(signal clk,a,b: in Boolean;
signal y : out Boolean)
begin
if clk='1' then
y <= a and b;
end if;
end;
begin
latch_1: my_latch (clock,input1,input2,outputA);
label_2: my_latch (clock,input1,input2,outputB);
end dataflow;
Example 3:
This example uses a concurrent conditional assignment to describe a
latch function for y. Note that y is used as an input to the conditional
statement as well as being used as the output:
architecture dataflow of latch is
begin
y <= a and b when clk else y;
end dataflow;
Flip-flops
The following four examples describe an edge sensitive flip-flop with
an AND function connected to its input. In all these cases the signal y
retains its current value unless the clock is changing.
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