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Noté. / 5. Basé sur avis des utilisateurs
How to Manage VHDL Design Hierarchies
VHDL Reference Manual 6-5
Configurations can also be used to re-map the ports of a component
and its lower-level entity, making it possible to substitute lower-level
entities that do not directly correspond to the component instance
being described at the higher-level. In this context, you can think of
configurations as being analogous to a configurable socket connecting
an IC package (the component) to a possibly mismatched set of
through-holes on a printed circuit board (which in turn corresponds to
a component reference in the higher-level entity).
The VHDL synthesizer supports the use of configurations, and allows a
configuration to be specified as the top-level design unit for synthesis
purposes. For more complete information about configurations, refer to
a standard VHDL text.
Blocks
Designs can be partitioned using either block statements or
component statements. While component statements are used to
create a hierarchy of connected components, block statements are
used to provide partitioning within a single architecture. Using block
statements to partition an architecture is analogous to using multiple
drawing sheets to enter a schematic-based design.
Block statements can be used to partition concurrent statements, as
in the following example:
architecture partitioned of some_design is
begin
<~><~><~>a_block: block
<~><~><~>begin
<~><~><~><~><~><~><~>-- concurrent statements here
<~><~><~>end block;
<~><~><~>another: block
<~><~><~>begin
<~><~><~><~><~><~><~>-- concurrent statements here
<~><~><~>end block;
end partitioned;
Blocks such as this have no special meaning for synthesis, and are not
frequently used in designs intended for synthesis.
Using Packages
Package declarations can be used to declare common types and
subprograms. For example:
package example_package is
type shared_enum is (first, second, third, last);
end example_package;
In order for the contents of a package to be visible from inside an
entity or an architecture, you need to place a use clause before the
entity declaration, as in the following example:
use work.example_package.all;
entity design_io is
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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