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How to Control the Implementation of VHDL
4-14 VHDL Reference Manual
Pinnum Attribute
You can specify pin and node numbers in the VHDL source file using
the custom attribute pinnum. special attribute is recognized by the
VHDL synthesizer and is written to the output for use by device fitting
software. This attribute has no other meaning to the VHDL synthesizer,
or to any other VHDL software (such as a simulator). The information
is simply passed on to the device fitting software.
To use the pinnum attribute:
1. Declare the pinnum attribute in the top-level entity as follows:
attribute pinnum : string;
2. Specify the value of pinnum attributes as strings, as in the
following example:
entity my_design is
port(a, b : in integer range 0 to 7;
c: bit_vector (3 to 5);
d: bit_vector (27 downto 25);
e: out Boolean);
attribute pinnum: string;
attribute pinnum of c: signal is "1,2,3";
attribute pinnum of d: signal is "6,5,4";
attribute pinnum of e: signal is "2";
end my_design;
To specify pin numbers for an array of signals:
You must consider the direction of the array. In the following example,
the pin numbers being assigned to each element of the arrays A and B
correspond to the index numbers for each array element:
entity toplevel is
port (Clock, reset: in std_logic;
A out std_logic_vector(1 to 3);
B out std_logic_vector(6 downto 4);
attribute pinnum: string;
attribute pinnum of Clock: signal is "1";
attribute pinnum of reset: signal is "19";
attribute pinnum of A: signal is "1,2,3";
attribute pinnum of B: signal is "6,5,4";
end toplevel;
If the pinnum attribute is applied to signals that are ports of the top-
level entity in the design (as in the above example), the values
specified in the attribute will be passed to the fitting software as pin
numbers. If the pinnum attribute is applied to signals that are internal
to an architecture, or are ports of a lower-level entity in the design,
the values will be ignored.
Note: Pin numbers that are entered using the pinnum attribute may
be overridden by device fitting software, if the software is unable to
map the design as specified. Most device fitting software includes
Project Navigator properties that can be used to control how pin
number mapping is performed. Refer to the device kit documentation
for more information.
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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