Microsoft AGB-00001 Spécifications

VHDL ReferenceManual096-0400-003March 1997

Language Structure2-2 VHDL Reference ManualStructure of a VHDL Design DescriptionThe basic organization of a VHDL design description is shown in Figur

How to Manage VHDL Design Hierarchies6-10 VHDL Reference Manual• The names that you use in your schematic for net or instancenames must be valid VHDL

How to Manage VHDL Design HierarchiesVHDL Reference Manual 6-11The generics library is also provided in source file form in thegeneric\vhdl subdirecto

How to Manage VHDL Design Hierarchies6-12 VHDL Reference Manual

VHDL Reference Manual A-1A. VHDL Quick ReferenceThis appendix contains basic reference information for VHDL syntax.For complete information, refer to

VHDL Quick ReferenceA-2 VHDL Reference ManualVHDL Syntax BasicsThe following code fragments illustrate the syntax of VHDL statements:Declarations-- OB

VHDL Quick ReferenceVHDL Reference Manual A-3Sequential Statements--IF STATEMENTif increment and not decrement then count := count +1;elsif not inc

VHDL Quick ReferenceA-4 VHDL Reference ManualSubprograms-- FUNCTION DECLARATION-- parameters are mode in-- return statements must return a valuefuncti

VHDL Quick ReferenceVHDL Reference Manual A-5Concurrent Statements-- BLOCK STATEMENTlabel5 : -- label is requiredblock -- type, signal,constant,

VHDL Quick ReferenceA-6 VHDL Reference Manual-- GENERATE STATEMENTlabel4 : -- label requiredfor i in 0 to 9 generate -- concurrent statements if

VHDL Quick ReferenceVHDL Reference Manual A-7Library Units-- PACKAGE DECLARATIONpackage globals is -- type,constant, signal ,subprogram declaration

Language StructureVHDL Reference Manual 2-3Library UnitsLibrary units (also known as design units) are the main components ofa VHDL description. They

VHDL Quick ReferenceA-8 VHDL Reference ManualAttributes♦ ATTRIBUTES DEFINED FOR TYPEST'base the base type of TT'left left bound of TT'r

VHDL Reference Manual B-1B. LimitationsVHDL is a technology-independent language and has a very largefeature set. Because the VHDL software is specif

LimitationsB-2 VHDL Reference Manual• A process sensitivity list must contain all signals that the process issensitive to.Constrained ExpressionsCerta

VHDL Reference Manual C-1C. VHDL for the ABEL-HDLDesignerThis Appendix compares ABEL-HDL and VHDL design strategies and isintended for the experience

VHDL for the ABEL-HDL DesignerC-2 VHDL Reference Manualport (pin_list: [mode] type [; pin_list: [mode] type ...]);The mode of a port in VHDL describes

VHDL for the ABEL-HDL DesignerVHDL Reference Manual C-3Figure C-1: Block Diagram for cntbuf DesignIn this example, the port statement defines the data

VHDL for the ABEL-HDL DesignerC-4 VHDL Reference Manual s1,s0 pin istype 'com'; "sum c0,c1 pin istype 'com&a

VHDL for the ABEL-HDL DesignerVHDL Reference Manual C-5To describe a registered function in structural or dataflow VHDL, youcan add a procedure to def

VHDL for the ABEL-HDL DesignerC-6 VHDL Reference Manualarchitecture adder_ff of add is signal f,g: bit; procedure dff(signal clk,d: bit;

VHDL for the ABEL-HDL DesignerVHDL Reference Manual C-7or, using the IEEE 1164 std_logic data types (which are described inmore detail in Chapter Erro

Language Structure2-4 VHDL Reference ManualEntityEntities contain the input and output definitions of the design. In VHDLdesigns that contain a hierar

VHDL for the ABEL-HDL DesignerC-8 VHDL Reference ManualPerhaps the most common mistake that is made by new VHDL users(who have had experience with PLD

VHDL for the ABEL-HDL DesignerVHDL Reference Manual C-9State MachinesDescribing State Machines in ABEL-HDLIn ABEL-HDL, you describe a state machine si

VHDL for the ABEL-HDL DesignerC-10 VHDL Reference Manuallibrary ieee;use ieee.std_logic_1164.all;entity machine is port (clk,reset: in std_logic;

VHDL for the ABEL-HDL DesignerVHDL Reference Manual C-11A Standard ABEL-HDL Design in VHDLThe VHDL source file, cntbuf.vhd, shows how one of the stand

VHDL for the ABEL-HDL DesignerC-12 VHDL Reference Manual end if; end process; process (Clk,OE,Count) -- Counter begin if

VHDL for the ABEL-HDL DesignerVHDL Reference Manual C-13Because IEEE 1164 std_logic_vector data types do not have a '+'operator defined for

VHDL for the ABEL-HDL DesignerC-14 VHDL Reference Manual

VHDL Reference Manual D-1D. ABEL-HDL LanguageReferenceThe information in this appendix is provided to help you read andinterpret the logic equations

How to Control the Implementation of VHDLD-2 VHDL Reference ManualDot extensionsIdentifier names used in ABEL-HDL equations may include dotextensions.

How to Control the Implementation of VHDLVHDL Reference Manual D-3DotExt.Pin-to-pinDescription.COM ü A combinational feedback from the flip-flopdata i

Language StructureVHDL Reference Manual 2-5ArchitectureThe architecture is the actual description of the design. If you thinkof an entity as a functio

How to Control the Implementation of VHDLD-4 VHDL Reference ManualDetailed Design Dot ExtensionsTable C-3 shows the dot extensions that are used to de

How to Control the Implementation of VHDLVHDL Reference Manual D-5Register Type ExtensionRequiredSupportedExtensionsDefinitionT-type flip-flopüü.clk.t

How to Control the Implementation of VHDLD-6 VHDL Reference ManualFigure C-1 through Figure C-9 show the effect of each dot extension.The actual sourc

How to Control the Implementation of VHDLVHDL Reference Manual D-7Figure C-4: Detailed Dot Extensions for an Inverted T-type Flip-flop ArchitectureFig

How to Control the Implementation of VHDLD-8 VHDL Reference ManualFigure C-7: Detailed Dot Extensions for an Inverted Latch with Active High LatchEnab

How to Control the Implementation of VHDLVHDL Reference Manual D-9Figure C-9: Detailed Dot Extensions for an Inverted Gated-clock D Flip-flop

How to Control the Implementation of VHDLD-10 VHDL Reference Manual

VHDL Reference Manual Index-1IndexAabs... 2-17, 3-6A

IndexIndex-2 VHDL Reference ManualCombinational logic ...3-2, C-3Componen

IndexVHDL Reference Manual Index-3FFeedback ... 3-26Fe

Language Structure2-6 VHDL Reference ManualStatementsThere are three basic kinds of statements in VHDL:• Declaration Statements• Concurrent Statements

IndexIndex-4 VHDL Reference ManualLibrary statement... 6-1, 6-6Logic e

IndexVHDL Reference Manual Index-5or ... 2-16

IndexIndex-6 VHDL Reference Manuallower-level ... 6-10top-l

IndexVHDL Reference Manual Index-viiTTextio package...2-1To

IndexIndex-8 VHDL Reference Manual

Language StructureVHDL Reference Manual 2-7Concurrent statements include the following:• Signal assignments (selected and conditional)• Component inst

Language Structure2-8 VHDL Reference Manualarchitecture behavior of some_thing isbegin process begin wait until clock; if (accelerato

Language StructureVHDL Reference Manual 2-9In these assignments, the variable named first_var is being assignedan integer value of 45 (For more inform

Language Structure2-10 VHDL Reference ManualLike initial values, delays specified using the optional after keywordare ignored by the synthesis compile

Language StructureVHDL Reference Manual 2-11Data TypesVHDL supports a variety of data types. The type of a variable, signal,or constant determines th

Synario Design Automation, a division of Data I/O, has made every attempt toensure that the information in this document is accurate and complete. Sy

Language Structure2-12 VHDL Reference ManualNumeric TypesThe numeric types consist of integer, floating point (real), andphysical types. Two encoding

Language StructureVHDL Reference Manual 2-13The encoding of integers in a binary format means that all ranges arerounded up to the nearest power of tw

Language Structure2-14 VHDL Reference ManualThe Std_ulogic and Std_logic Data TypesStd_ulogic (which is the base type of the more-commonly usedresolve

Language StructureVHDL Reference Manual 2-15 process(clk) begin if clk and clk'event then p <= p + 1; end if;

Language Structure2-16 VHDL Reference Manual if clk = '1' and clk'event then p <= To_Vector(2,To_Integer(p) + 1);

Language StructureVHDL Reference Manual 2-17Arithmetic OperatorsArithmetic operators are used to create arithmetic functions. VHDLprovides the followi

Language Structure2-18 VHDL Reference ManualWhen used with an array, the 'high attribute has a value of thehighest array index: type my_array

VHDL Reference Manual 3-13. How to WriteSynthesizable VHDLThe hardware implementation of a design written in VHDL depends onmany factors. Coding conv

How to Write Synthesizable VHDL3-2 VHDL Reference ManualIn addition, a VHDL design written for simulation may use enumeratedtypes to represent the enc

How to Write Synthesizable VHDLVHDL Reference Manual 3-3Constants and TypesThe context in which an operator is used effects the generatedcircuitry. Us

VHDL Reference Manual iiiTable of Contents1. Introduction ...

How to Write Synthesizable VHDL3-4 VHDL Reference Manual m <= (a and b) or e; --concurrent signal assignments e <= c xor d;end example;Exa

How to Write Synthesizable VHDLVHDL Reference Manual 3-5Relational OperatorsVHDL provides relational operators as shown in Table 3-1.Table 3-1: Relati

How to Write Synthesizable VHDL3-6 VHDL Reference ManualArithmetic OperatorsThe arithmetic operators in VHDL are defined for numeric types(integer and

How to Write Synthesizable VHDLVHDL Reference Manual 3-7The absolute (abs) operator is not expensive to implement. The **operator is only supported wh

How to Write Synthesizable VHDL3-8 VHDL Reference ManualShift OperatorsThe shift operators in VHDL are defined for the types bit and boolean.In additi

How to Write Synthesizable VHDLVHDL Reference Manual 3-9Concurrent Statement: Conditional Signal AssignmentThe following is an example of a conditiona

How to Write Synthesizable VHDL3-10 VHDL Reference Manual end process;end example;Case StatementLike the with statement, VHDL requires that all the

How to Write Synthesizable VHDLVHDL Reference Manual 3-11Describing Replicated LogicVHDL provides the following subprograms and looping constructs for

How to Write Synthesizable VHDL3-12 VHDL Reference ManualA procedure differs from a function in that there is no return value, andthe arguments of the

How to Write Synthesizable VHDLVHDL Reference Manual 3-13While statements are also supported by the VHDL synthesizer, withthe constraint that the loop

Table of Contentsiv VHDL Reference ManualDescribing Combinational Logic...3-2Constants and Types ...

How to Write Synthesizable VHDL3-14 VHDL Reference ManualFigure 3-5: Loop and Subprogram StatementsGen2: if test_flag = 1 generate test_pins <=

How to Write Synthesizable VHDLVHDL Reference Manual 3-15Describing Sequential LogicThis section describes in detail how various kinds of registeredse

How to Write Synthesizable VHDL3-16 VHDL Reference Manualprocess(clk) begin if clk='1' then y <= a; else y <= b

How to Write Synthesizable VHDLVHDL Reference Manual 3-17Alternatively, you can describe a latch as transparent low by invertingthe conditional logic:

How to Write Synthesizable VHDL3-18 VHDL Reference Manualprocess(clk) begin if rising_edge(clk) then y <= a; end if;end process;In

How to Write Synthesizable VHDLVHDL Reference Manual 3-19LatchesThe following three examples each describe a level sensitive latch withan and function

How to Write Synthesizable VHDL3-20 VHDL Reference ManualExample 1:A process statement for a flip-flop is identical to the first latchexample, above,

How to Write Synthesizable VHDLVHDL Reference Manual 3-21Note: In examples 1, 3 and 4, above, the clk and clk'eventcondition expression can be r

How to Write Synthesizable VHDL3-22 VHDL Reference ManualSynchronous Set/ResetTo add the behavior of synchronous set or reset you can simply add acond

How to Write Synthesizable VHDLVHDL Reference Manual 3-23 elsif clk='1' and clk'event then y <= a and b; end if;end pro

Table of ContentsVHDL Reference Manual vSelecting a Base Data Type ... 4-10Using the Integer Type .

How to Write Synthesizable VHDL3-24 VHDL Reference ManualYou can combine the asynchronous reset and preset to create anasynchronous load:library ieee;

How to Write Synthesizable VHDLVHDL Reference Manual 3-25Template State MachineThe recommended method for describing synthesizable state machinesin VH

How to Write Synthesizable VHDL3-26 VHDL Reference ManualThis state machine description includes two combinational outputs(port comb_outputs) that dec

How to Write Synthesizable VHDLVHDL Reference Manual 3-27architecture example of some_entity isbegin process (clk) begin if clk = '1&a

How to Write Synthesizable VHDL3-28 VHDL Reference ManualTypes of State MachinesClassical state machines can be classified as Moore or Mealy machines.

How to Write Synthesizable VHDLVHDL Reference Manual 3-29A more compact description of this architecture could be written asfollows:architecture moore

How to Write Synthesizable VHDL3-30 VHDL Reference ManualInput RegistersIf the system timing requires no logic between the registers and theinput (a s

How to Write Synthesizable VHDLVHDL Reference Manual 3-31Mealy state machines can be written more clearly, however, if threeprocesses are used in the

How to Write Synthesizable VHDL3-32 VHDL Reference ManualPerhaps the most common mistake made by new VHDL users(particularly those who have had experi

VHDL Reference Manual 4-14. How to Control theImplementation of VHDLUsing Enumerated TypesEnumerated types are very important in VHDL, and are the on

Table of Contentsvi VHDL Reference ManualReserved Words ...A-1VHDL Syntax Basics.

How to Control the Implementation of VHDL4-2 VHDL Reference ManualThe type std_ulogic (from which std_logic is derived) is also anenumerated type, an

How to Control the Implementation of VHDLVHDL Reference Manual 4-3An example of a state machine design that uses enum_encoding tospecify a particular

How to Control the Implementation of VHDL4-4 VHDL Reference ManualOf these four possible values, only the 1 and 0 result in logic beinggenerated for a

How to Control the Implementation of VHDLVHDL Reference Manual 4-5type cpu_op is (execute,load, store);Two wires with the values 00, 01, and10; the bi

How to Control the Implementation of VHDL4-6 VHDL Reference ManualControlling Output InversionMany common PLDs feature inverted registered outputs, or

How to Control the Implementation of VHDLVHDL Reference Manual 4-7 o1,o2: out std_logic);end polarity;architecture inversion of polarity is

How to Control the Implementation of VHDL4-8 VHDL Reference ManualControlling Feedback PathsIf the design description specifies feedback, then the VHD

How to Control the Implementation of VHDLVHDL Reference Manual 4-9entity counter1 is port (clock: in Boolean; count: inout integer range 0

How to Control the Implementation of VHDL4-10 VHDL Reference ManualSelecting a Base Data TypeAn important consideration when starting a VHDL design pr

How to Control the Implementation of VHDLVHDL Reference Manual 4-11The problem with this code is that whenever the sum of a and bexceeds 7, a fatal er

VHDL Reference Manual 1-11. IntroductionThis manual discusses VHDL and the Synario Programmable ICSolution. This manual is intended to supplement th

How to Control the Implementation of VHDL4-12 VHDL Reference ManualUsing IEEE 1076.3 Unsigned/Signed TypesIn late 1995 the IEEE 1076.3 commitee appro

How to Control the Implementation of VHDLVHDL Reference Manual 4-13Synthesis of Don't CaresIf you are designing using the type std_logic as your

How to Control the Implementation of VHDL4-14 VHDL Reference ManualPinnum AttributeYou can specify pin and node numbers in the VHDL source file usingt

How to Control the Implementation of VHDLVHDL Reference Manual 4-15To specify node numbers:1. Declare the signal in the entity (not the architecture).

How to Control the Implementation of VHDL4-16 VHDL Reference ManualIf you will be assigning properties to signals that are part of non-binary data typ

How to Control the Implementation of VHDLVHDL Reference Manual 4-17 or2: out std_logic); end component; attribute macrocell: boolean;

How to Control the Implementation of VHDL4-18 VHDL Reference ManualEnum_encoding AttributeThe enum_encoding attribute allows you to override the defau

VHDL Reference Manual 5-15. VHDL Datapath SynthesisA common problem with using VHDL synthesis for FPGA and PLDdesign is that synthesis tools often to

VHDL Datapath Synthesis5-2 VHDL Reference ManualHow Inferencing WorksInferencing is currently supported for the following macros:♦ ADD_SUB♦ MULT♦ COUN

VHDL Datapath SynthesisVHDL Reference Manual 5-3To View the Results of Inferencing:1. Select the Synthesize Logic process, and click on the Properties

Introduction1-2 VHDL Reference Manual

VHDL Datapath Synthesis5-4 VHDL Reference ManualIf this happens because of an inferred macrofunction, turn LPMinferencing off. If it happens because o

VHDL Datapath SynthesisVHDL Reference Manual 5-5COUNTERInference of the COUNTER macro works very similarly to that for theADD_SUB. Examples of code th

VHDL Datapath Synthesis5-6 VHDL Reference ManualCOMPAREThe COMPARE macrofunction will be inferred from the use of any of thefollowing relational opera

VHDL Datapath SynthesisVHDL Reference Manual 5-7Inferencing DetailsThis section provides additional details on inferencing.Supported TypesInferencing

VHDL Datapath Synthesis5-8 VHDL Reference ManualResource SharingConsider the following simple ALU:p0: process(operand0, operand1, operand2, opcode)beg

VHDL Datapath SynthesisVHDL Reference Manual 5-9Instantiation DetailsIf you are planning to do direct instantiation of the Synario GenericDatapth mac

VHDL Datapath Synthesis5-10 VHDL Reference Manuali_addsub0: g_add_sub generic map (width => 8, representation => "UNSIGNED") port ma

VHDL Datapath SynthesisVHDL Reference Manual 5-11to up counter.Aset Optional Logic 0 Asynchronous set input Sets all Q outputs highAclr Optional Logic

VHDL Datapath Synthesis5-12 VHDL Reference ManualG_COUNTER also has the following generics:Generic Usage Description CommentsWidth Required The width,

VHDL Datapath SynthesisVHDL Reference Manual 5-13G_MULTThe following table describes the ports of the G_MULT:Port Usage DefaultValueDescription Commen

VHDL Reference Manual 2-12. Language StructureVHDL is a hardware description language (HDL) that contains thefeatures of conventional programming lan

VHDL Datapath Synthesis5-14 VHDL Reference ManualG_ROMAt the current time G_ROM is never inferred. It may be instantiated,but is only supported for Al

VHDL Reference Manual 6-16. How to Manage VHDLDesign HierarchiesManaging Large DesignsThis section shows you how to use partitioning and designmanage

How to Manage VHDL Design Hierarchies6-2 VHDL Reference ManualComponentsVHDL design entities can be referenced from other architectures ascomponents.

How to Manage VHDL Design HierarchiesVHDL Reference Manual 6-3In this example, the architecture of addmult contains a declaration oftwo components, ad

How to Manage VHDL Design Hierarchies6-4 VHDL Reference ManualWhen you simulate a design consisting of multiple VHDL files, youmust compile the design

How to Manage VHDL Design HierarchiesVHDL Reference Manual 6-5Configurations can also be used to re-map the ports of a componentand its lower-level en

How to Manage VHDL Design Hierarchies6-6 VHDL Reference Manual ...end design_io;Placing a use clause before an entity causes the contents of thespe

How to Manage VHDL Design HierarchiesVHDL Reference Manual 6-7Using Packages For Common DeclarationsTo define common declarations (such as types, subt

How to Manage VHDL Design Hierarchies6-8 VHDL Reference ManualUsing Design LibrariesIn most VHDL simulation environments, design libraries are areas i

How to Manage VHDL Design HierarchiesVHDL Reference Manual 6-9Work is the default name of the current library. The work library iswhere, in a simulati