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How to Control the Implementation of VHDL

4-4 VHDL Reference Manual

Of these four possible values, only the 1 and 0 result in logic being

generated for a signal, so an element of an enumerated type that is

defined using any of the four characters results in only a single wire

being generated. For enumerated type elements that are defined using

the “-” character, the VHDL synthesizer generates a don’t-care for the

signal. This often results in better logic optimization. Enumerated type

elements that are defined using the Z character result in output enable

logic being generated for the associated signal. (This matches the

convention for output enables commonly used in simulation

environments.)

The enum_encoding attribute must be entered as a single string

value. Strings in VHDL cannot span multiple lines, so to enter a long

enum_encoding value, you must concatenate multiple strings using

the ’&’ (concatenate) operator as shown in the following example:

attribute enum_encoding of states: type is

"00101 00000 10000 00100 10100 " &

"01100 01000 10101 10001 11000 " &

"10011 00011 00001 01101 01001 11001";

“One hot” Enumeration

In addition to the enumeration values shown above, the VHDL

synthesizer supports a special type of enumeration attribute value for

state machines. The following statements define an enumerated type

for a state machine and specify that the state machine is to be

encoded using a one hot (one bit active per state) representation:

type machine is (init, s1, s2, s3, s4);

attribute enum_encoding of machine : type is "one hot";

In this example, the five states of the machine (init, s1, s2, s3, and

s4) are encoded automatically with the values 00001, 00010, 00100,

01000, and 10000, respectively by the VHDL synthesizer. When used

as next and previous state values in a subsequent case statement, the

value of the type is decoded using only that bit that is “hot” (has a

value of 1) for each enumerated value. This results in a dramatic

decrease in the amount of decoding logic required for each condition in

the case statement logic, at the expense of a few additional registers.

Note: One hot encoding is particularly effective when you are

generating circuits intended for implementation in register-rich

architectures such as FPGAs.

Don’t-cares and Enumerated Types

Unused encodings result in don’t-care conditions, which allow the

VHDL synthesizer to perform additional logic optimizations. Subtypes

use the element encodings of their base, and may result in additional

don’t-care conditions being generated. For example:

The declaration: Is synthesized as:

type direction is

(left, right, up, down);

Two wires with the values 00, 01, 10,

and 11.

1 2 ... 57 58 59 60 61 62 63 64 65 66 67 ... 143 144

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