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How to Manage VHDL Design Hierarchies

6-4 VHDL Reference Manual

When you simulate a design consisting of multiple VHDL files, you

must compile the design from the bottom up, beginning with the VHDL

files containing the lowest-level design entities (those that contain no

references to other VHDL design units). The VHDL simulator does not

allow VHDL source files to be compiled if they contain references to

lower-level design entities that have not yet been compiled.

Note: The Project Navigator expects the entity and architecture

declarations for each design entity to be located in the same source

file.

Using A Single Hierarchical VHDL File

If you choose to enter your design as a single VHDL source file,

however, the VHDL synthesizer will attempt to flatten the entire design

into a non-hierarchical form. When doing this, the VHDL synthesizer

will assume that the last entity (or configuration declaration)

encountered in the VHDL source file is the top-level design entity. If

the top-level design entity is not the last entity or architecture in the

file, then you must specify the name of the actual top-level design

entity by setting the Top-Level Entity property in the Project Manager.

Configurations

Configurations are one of five primary design units in VHDL (the others

being entities, architectures, package declarations and package

bodies). During synthesis or simulation, you may choose to have a

configuration statement represent the highest level design unit in your

design instead of the top-level entity. When you process a design with

a configuration statements as the highest level design unit, the

configuration statement provides the necessary information to define

the design, in terms of the relationships between all the other design

units and their references to lower-level design units (entities,

architectures, and component references to lower-level entities and

architectures).

For structural VHDL (designs with many components arranged in a

hierarchy) it is useful to think of the configuration statement as a parts

list. The configuration statement may contain statements associating

each component instance in the design with a specific architecture

(perhaps allowing a different architecture to be used for simulation

than is used for synthesis) or may specify generics (compile-time

values) that configure components prior to their use. (One common

use of generics in this way is to pass delay values into an architecture

prior to simulation.)

Note: Generics are fully supported in the VHDL synthesizer, but are

not described in this manual. Refer to a standard VHDL text for

information about this language feature.

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