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Language Structure
VHDL Reference Manual 2-13
The encoding of integers in a binary format means that all ranges are
rounded up to the nearest power of two. This means that if shorter had
been declared as:
subtype shorter is short range 0 to 16;
then the result would have been the same after synthesis. Objects
declared type of type integer without a range constraint will be
synthesized into 32 wires.
The are two predefined subtypes of integer. Subtype natural is
defined as non-negative integer, while subtype positive is defined as
a non-negative and non-zero integer.
Other Types
The types bit, Boolean, character, std_ulogic and std_logic are
enumerated types. Enumerated types are discussed in the following
subsection. The type bit_vector is an array, as is the type
std_logic_vector.
• Bit , std_logic and std_ulogic types are synthesized to one wire.
• Character types are synthesized to seven wires.
• Boolean types are synthesized to one wire.
• Array and record types are composites, and are treated as
collections of their elements. Subtypes of composite types are
treated as collections of the elements of the subtype only.
Enumerated Types
An enumerated type in VHDL is a special kind of data type that has a
symbolic value. A good example of where an enumerated type signal
would be used is in a state machine, in which symbolic values are used
to represent unique states of the machine:
type machine_state is (Init, Ready, Xmit1, Xmit2, Xmit3, Xmit4);
signal present_state, next_state: machine_state;
Many of the common data types used in VHDL, such as bit, Boolean,
character, and std_ulogic, are actually enumerated types defined in a
library such as std or ieee. Bit, Boolean, and character are all
enumerated types that are predefined in std.vhd.
When synthesized, enumerated types result in a binary encoding,
unless the enum_encoding attribute has been used to specify
alternate values for each element of the type. In the absence of the
enum_encoding attribute, elements in the enumerated type are
assigned numeric values from left to right, with the value of the
leftmost element being zero.
By default, the number of wires generated to encode an enumerated
type will be the smallest possible n, where the number of elements is
2
n
. (It will, for example, require three wires to represent an
enumerated type with more than four but less than nine different
values.)
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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