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VHDL for the ABEL-HDL Designer

VHDL Reference Manual C-3

Figure C-1: Block Diagram for cntbuf Design

In this example, the port statement defines the data types. (This

example uses the IEEE 1164 std_logic data types. These data types

are described in detail in Chapter Error! Reference source not

found., “Error! Reference source not found..”) The VHDL pinnum

attribute statement is then used to assign actual pin numbers to the

design's I/O ports:

library ieee;

use ieee.std_logic_1164.all;

entity cntbuf is

port(Dir: in std_logic;

Clk,Clr,OE: in std_logic;

A,B: inout std_logic_vector (0 to 1);

Q: inout std_logic_vector (3 downto 0));

attribute pinnum : string; -- Define the attribute

attribute pinnum of Clk: signal is "1";

attribute pinnum of Clr: signal is "2";

attribute pinnum of Dir: signal is "3";

attribute pinnum of OE: signal is "11";

attribute pinnum of A: signal is "13,12";

-- Assigns A_0_ to 13, A_1_ to 12

attribute pinnum of B: signal is "19,18";

-- Assigns B_0_ to 19, B_1_ to 18

attribute pinnum of Q: signal is "17,16,15,14";

end cntbuf;

In this design, the bit vectors A, B, and Q must be given a list of pin

numbers according to the width of their data types. The order of the

list of pin numbers is significant. If the VHDL bit vectors are ordered

from least- to most-significant bit (LSB to MSB) using the to range

specifier, then the mapping signals to pins is also LSB to MSB (A(0)

would be mapped to pin 13 and A(1) would be mapped to pin 12).

Combinational Logic

Describing Combinational Logic in ABEL-HDL

In ABEL-HDL, you use the combinational assignment operator ('=') to

specify combinational logic in the Equations section of your program.

The following ABEL-HDL design uses equations to describe the function

of a simple 2-bit adder circuit:

module add

a0,a1,b0,b1 pin; "operands A and B

1 2 ... 110 111 112 113 114 115 116 117 118 119 120 ... 143 144

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Microsoft AGB-00001 Spécifications Page 115