Microsoft AGB-00001 Spécifications Page 98
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
How to Manage VHDL Design Hierarchies
6-8 VHDL Reference Manual
Using Design Libraries
In most VHDL simulation environments, design libraries are areas in
which pre-compiled (analyzed) design units are stored. An good
example of such a library is the IEEE library, which is pre-compiled into
a library accessible to the VHDL simulator. The form that the pre-
compiled library takes is dependent upon the simulator being used,
and compiled libraries are generally not compatible between different
simulator programs.
The VHDL synthesizer, on the other hand, implements libraries as
source files that are read in and synthesized as they are encountered
in a higher-level VHDL source file (as library statements). This means
that a library such as the IEEE library must exist as a VHDL source file,
and must be accessible to the VHDL synthesizer during the compilation
process. The VHDL source code for the IEEE library, for example, is
provided in the file ieee.vhd.
Note: The VHDL implicit library std does not have to be referenced in
a library or use statement. The library std is contained in the file
std.vhd.
Library Search Paths
When the VHDL synthesizer encounters a library statement, it
attempts to find a corresponding VHDL source file (one with a name
matching the referenced library name) in the current directory (the
project directory). If a VHDL source file with the appropriate name is
not found in the current directory on your system, the VHDL
synthesizer will attempt to find the referenced VHDL source file in the
library area (normally ./lib5/) within the Project Navigator installation
directory.
If you create library files that will be shared between multiple projects,
you may want to place those files in the library area, rather than make
local copies in each project directory.
The Work Library
The differences in library implementations between most simulation
environments and the VHDL synthesizer does not normally make any
difference; library files are read in by the synthesizer as needed, and
the library and use statements function normally. The only exception
is in the treatment of the default library, work.
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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