Microsoft AGB-00001 Spécifications télécharger pdf (Page 22)

Language Structure

2-14 VHDL Reference Manual

The Std_ulogic and Std_logic Data Types

Std_ulogic (which is the base type of the more-commonly used

resolved type std_logic) is a data type defined by IEEE standard 1164,

and defined in the file ieee.vhd. Std_ulogic is an enumerated type, and

has the following definition (from ieee.vhd):

type std_ulogic is (

'U', -- Uninitialized

'X', -- Forcing Unknown

'0', -- Forcing 0

'1', -- Forcing 1

'Z' -- High Impedance

'W' -- Weak Unknown

'L' -- Weak 0

'H' -- Weak 1

'-' -- Don't care

);

The std_ulogic (or std_logic) data type is very important for both

simulation and synthesis. Std_logic includes values that allow you to

accurately simulate such circuit conditions as unknowns and high-

impedance states. For synthesis purposes, the high-impedance and

don't-care values provide a convenient and easily recognizable way to

represent three-state enables and don't-care logic. For synthesis, only

the values ‘0’, ‘1’, ‘Z’, and ‘-’ have meaning and are supported. The

version of std_logic_1164 defined in the file ieee.vhd includes an

enum_encoding attribute that results in each object of type std_ulogic

or std_logic being synthesized into a single wire.

User Defined Types and Subtypes

In addition to the standard types, you can define your own types which

may be scalars, arrays, or records. VHDL also allows subtypes, which

are simply a mechanism to define a subset of a type.

The use of types other than bit and bit_vector (or std_logic and

std_logic_vector) can make your design much easier to read. It is good

VHDL coding practice to put all your type definitions in a package and

make the contents of that package visible with a use statement. The

following example shows how a subtype of integer is defined in a

package and referenced in the rest of the design:

package type_defs is

subtype very_short is integer range 0 to 3;

end type_defs;

use work.type_defs.all; -- use clause

entity counter is

port (clk: in Boolean; p: inout very_short);

end counter;

architecture behavior of counter is

begin

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 143 144

Commentaires sur ces manuels

Pas de commentaire

Microsoft AGB-00001 Spécifications Page 22

Commentaires sur ces manuels

Produits connexes et manuels pour Claviers Microsoft AGB-00001