Microsoft AGB-00001 Spécifications Page 50
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
How to Write Synthesizable VHDL
3-24 VHDL Reference Manual
You can combine the asynchronous reset and preset to create an
asynchronous load:
library ieee;
use ieee.std_logic_1164.all;
library dataio;
use dataio.std_logic_ops.all;
entity asyn_load_cnt is
port(
clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
preset : in std_logic;
load : in std_logic;
d : in std_logic_vector(7 downto 0);
q : buffer std_logic_vector(7 downto 0));
end;
architecture behavioral of asyn_load_cnt is
signal next_q : std_logic_vector(7 downto 0);
begin
next_q <= q + '1';
process(clk, reset, preset, load, d)
begin
for i in q'range loop
if (reset = '1') or (load = '1' and d(i) = '0') then
q(i) <= '0';
elsif (preset = '1') or (load = '1' and d(i) = '1') then
q(i) <= '1';
elsif (rising_edge(clk)) then
if (ce = '1') then
q(i) <= next_q(i);
end if;
end if;
end loop;
end process;
end behavioral;
This logic defines an 8 bit up counter, with asynchronous reset, preset,
load, and clock enable. Since the VHDL synthesis compiler requires
that the value assigned by the reset or preset condition be a constant
expression, a loop construct inside the process generates the logic for
each flip-flop individually.
Describing Finite State Machines
This section describes the relationship between various types of finite
state machines (FSMs), the VHDL description methods that are most
commonly used to specify them, and the logic that is generated as a
result of synthesis. Each example illustrates a single state machine.
(This is not a constraint of VHDL or the VHDL synthesizer, just a
simplification. Multiple state machines are supported in VHDL, and the
different machines can operate independently using multiple clocks.)
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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