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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
How to Write Synthesizable VHDL
VHDL Reference Manual 3-27
architecture example of some_entity is
begin
process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
c <= '0';
else
c <= a and c; -- c is fed back directly
end if;
end if;
end process;
end example;
This method eliminates the intermediate signal b.
Feedback on Variables
Variables exist within a process, and preserve their data as processes
suspend and reactivate. Feedback is created whenever variables are
used (placed on the right hand side of an assignment or used in a
conditional statement) before they are assigned (placed on the left
hand side of an assignment.)
Feedback paths typically contain registers, so to use feedback in a
process you will usually want to insert a conditional statement that
implies a clock into the process. The following example shows how
registered feedback is created (to form a counter function) from the
use of a variable in a process:
process (clk)
variable Count: integer range 0 to 255;
begin
if clk = '1' and clk'event then
if reset = '1' then
Count := 0;
elsif Count = 255 then
Count := 0;
else
Count := Count + 1; -- Counter feeds back
end if;
end if;
C <= Count;
end process;
In this example, the counter output (C) is assigned the value of the
variable Count, creating an 8-bit counter on the design output. In the
above example, eight flip-flops are generated for the output C, and the
feedback logic for variable Count is folded into the logic for C.
Note: Variables only imply registers when used within process
statements. If a variable is declared inside a function or procedure,
the variable is local to the subprogram; it exists only within the scope
of the subprogram.
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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