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Noté. / 5. Basé sur avis des utilisateurs
How to Control the Implementation of VHDL
VHDL Reference Manual 4-3
An example of a state machine design that uses enum_encoding to
specify a particular (non-sequential) encoding of state values is
presented in the tutorials chapter of the VHDL Entry manual. The
prep4 (complex state machine) example presented in that chapter
uses enum_encoding to specify an encoding that is optimized for a
complex PLD implementation, as well as using explicit assignments to
the ’-’ value to include don’t-care information about the circuit’s
outputs.
An example of resolving multi-valued logic can be found in the
definition for the std_ulogic data type (upon which the type
std_logic is based). As described above, the std_ulogic data type is
defined in the package std_logic_1164 (which is located in the file
ieee.vhd) to have nine possible values: ’U’, ’X’, ’0’, ’1’, ’Z’, ’W’, ’L’, ’H’
and ’-’. If these nine values were given the default binary
enumerations, then any signal of type std_ulogic (or the derived type
std_logic) would require four wires when synthesized, rather than the
intended single wire. To solve this dilemma, the following
enum_encoding attribute specification (which is provided in
ieee.vhd) results in a single-bit (and non-unique) encoding for each
value of the std_ulogic data type:
attribute enum_encoding: string;
attribute enum_encoding of std_ulogic: type is
"- - 0 1 Z - - - -"
Enum_encoding is a custom attribute recognized by the VHDL
synthesizer (and ignored by other tools, such as simulators) that maps
the elements of an enumerated type into an actual encoding, using 1
of 4 possible enumeration values. The enumerations for each type are
listed in the attribute string (with entries separated by a space
character) and may consist of one or more of the characters shown in
Table 4-1.
Table 4-1: Logical values for enumeration characters
Enumeration
character
Logic Value
0 0
1 1
- Don’t care (for logic optimization)
Z High impedance (implies an output enable)
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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