How to Control the Implementation of VHDL
VHDL Reference Manual 4-9
entity counter1 is
port (clock: in Boolean;
count: inout integer range 0 to 7;
end counter1;
architecture pin_feedback of counter1 is
begin
process (clock)
begin
if clock and clock'event then
if count = 7 then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;
end pin_feedback;
Note: Mode inout should only be used to describe true directional
ports—those that have an output enable function associated with
them. Using inout to describe signals that are simply fed back to
create circuits such as counters is not recommended.
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