Microsoft AGB-00001 Spécifications Page 87
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
VHDL Datapath Synthesis
VHDL Reference Manual 5-11
to up counter.
Aset Optional Logic 0 Asynchronous set input Sets all Q outputs high
Aclr Optional Logic 0 Asynchronous clear input Sets all Q outputs low
Aconst Optional Logic 0 Asynchronous set/clear input Sets the Q output to the value
of the AVALUE generic. If used,
neither the Aset or Aclr inputs
can be used.
Aload Optional Logic 0 Asynchronous load input Sets the Q output to the value
of the Data input.
Sset Optional Logic 0 Synchronous set input Sets all Q outputs high on the
next rising edge of Clock with
Enable high.
Sclr Optional Logic 0 Synchronous clear input Sets all Q outputs high on the
next rising edge of Clock with
Enable high.
Sconst Optional Logic 0 Synchronous set/clear input Sets the Q output to the value
of the SVALUE generic on the
next rising edge of Clock with
Enable high. If used, neither the
Sset or Sclr inputs can be used.
Sload Optional Logic 0 Synchronous load input Sets the Q output to the value
of the Data input on the next
rising edge of Clock with Enable
high. If used, the Data input
must be used.
Testenab Optional Logic 0 Active high test enable. When this input is high,
COUNTER enters a test mode
and will serially shift data
through from the Testin input to
the Testout output.
Testin Optional Logic 0 Serial test data input The value on this input is shifted
into Q(0) on the rising edge of
Clock with Testenab active.
Testout Optional None Serial test data output This output is always equal to
Q(WIDTH-1).
Q Optional None Registered Counter output Size equals WIDTH generic.
Eq Optional None Asynchronous decode of the Q
output.
Size equals 2**WIDTH generic.
Notes:
1. Most targets do not support the Testenab, Testin, Testout, Aconst,
Aload, and Sconst ports.
2. The Eq port, if used, will be 2**WIDTH bits wide. The compile time
will grow exponentially with the width of this port; therefore we
recommend that if you use this port that you do not set WIDTH >
6. If necessary, you can cascade individual G_COUNTERs together
to create wider counter functions.
- VHDL Reference 1
- Table of Contents 3
- 1. Introduction 7
- Introduction 8
- 1-2 VHDL Reference Manual 8
- 2. Language Structure 9
- Architecture 13
- Configuration 13
- Statements 14
- Data Objects 16
- Constants 17
- Data Types 19
- Numeric Types 20
- Other Types 21
- Enumerated Types 21
- Types and Logic Synthesis 23
- Type Conversions 23
- Operators 24
- VHDL Attributes 25
- variable info : my_array; 26
- signal clock : Boolean; 26
- 3. How to Write 27
- Constants and Types 29
- Logical Operators 29
- Relational Operators 31
- Arithmetic Operators 32
- Describing Conditional Logic 34
- If Statement 35
- Case Statement 36
- Describing Replicated Logic 37
- Loop Statements 38
- Generate Statements 39
- Describing Sequential Logic 41
- Wait Statement 44
- Flip-flops 45
- Gated Clocks and Clock Enable 47
- Synchronous Set/Reset 48
- Asynchronous Set/Reset 48
- Asynchronous Reset/Preset 49
- Template State Machine 51
- Feedback Mechanisms 52
- Types of State Machines 54
- Moore Machine 54
- Mealy Machine 56
- 4. How to Control the 59
- Synthesis of Enumerated Types 60
- Enum_encoding attribute 60
- “One hot” Enumeration 62
- Describing Output Enables 63
- Controlling Output Inversion 64
- VHDL Reference Manual 4-7 65
- Controlling Feedback Paths 66
- Selecting a Base Data Type 68
- Synthesis of Don't Cares 71
- Pinnum Attribute 72
- Property Attribute 73
- Macrocell Attribute 74
- Critical Attribute 75
- Enum_encoding Attribute 76
- 5. VHDL Datapath Synthesis 77
- How Inferencing Works 78
- Inferencing Details 83
- Instantiation Details 85
- 6. How to Manage VHDL 91
- Components 92
- Components And Synthesis 93
- Configurations 94
- Using Packages 95
- Package Visibility Rules 96
- Design Libraries 96
- Using Design Libraries 98
- Using Schematics With VHDL 99
- 6-12 VHDL Reference Manual 102
- A. VHDL Quick Reference 103
- VHDL Syntax Basics 104
- Sequential Statements 105
- Subprograms 106
- Concurrent Statements 107
- VHDL Quick Reference 108
- A-6 VHDL Reference Manual 108
- Library Units 109
- Attributes 110
- B. Limitations 111
- Ignored Constructs 112
- C. VHDL for the ABEL-HDL 113
- Pin and Node Numbers 114
- Combinational Logic 115
- Registers 116
- Avoiding Unwanted Latches 119
- State Machines 121
- Design I/O 124
- Registered Logic 124
- C-14 VHDL Reference Manual 126
- D. ABEL-HDL Language 127
- Dot extensions 128
- VHDL Reference Manual D-7 133
- VHDL Reference Manual D-9 135
- D-10 VHDL Reference Manual 136
- Index-8 VHDL Reference Manual 144
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